The present invention relates generally to hybrid delta-sigma/SAR analog to digital converters (ADCs) of the type described in above-mentioned commonly assigned patent application Ser. No. 11/738,566. More particularly, the present invention relates to improvements which provide minimum integrator output swing, operation with very low power supply voltage, reduced quiescent current, and high accuracy even though the integrated circuit hybrid delta-sigma/SAR ADC is fabricated using low voltage “leaky” manufacturing processes.
Various analog to digital data converters and conversion techniques have been developed over the years for converting electrical signals from an analog domain to a digital domain. In general, the process of analog to digital conversion includes sampling an analog signal and comparing the sampled analog signal to a threshold value. A binary result is recorded depending upon the result of the comparison. The process of comparing the sample against a threshold may be repeated a number of times with each successive comparison using a different threshold and residue of the sample. The number of iterations typically affects the noise level of any result as well as the resolution of the ultimate digital signal.
Some analog to digital converters rely on delta-sigma modulation techniques. FIG. 1A is a conceptual diagram of a first order delta-sigma analog to digital converter 100. Analog to digital converter 100 includes an operational amplifier 110, a comparator 120, and a counter 130. A positive input of operational amplifier 110 is electrically coupled to ground. A negative input of operational amplifier 110 is electrically coupled to a reference sample capacitor 156 and an input sample capacitor 166. Reference sample capacitor 156 is electrically coupled to a negative version of a voltage reference 150 via a switch 152, and to ground via a switch 154. Input sample capacitor 166 is electrically coupled to a voltage input 160 via a switch 162 and to ground via a switch 164. An integrating capacitor 116 is electrically coupled between the output and the negative input of operational amplifier 110 by way of a switch 114. Another switch 112 allows for shorting the output of operational amplifier 110 to the negative input thereof.
In operation, voltage input 160 is sampled by closing switch 162 and switch 112. This allows input sample capacitor 166 to be charged to a level reflecting voltage input 160. The charge from input sample capacitor 166 is then transferred to integrating capacitor 116 by opening switch 162 and switch 112, and closing switch 114 and switch 164. This results in an output from operational amplifier 110 at the input of comparator 120. If the gain of operational amplifier 110 is unity, the output is approximately equal to voltage input 160. The output is compared with voltage reference 150. If the result is a logic ‘0’, counter 130 is not incremented. In the next pass, voltage input 160 is again sampled by closing switch 162 and switch 112. Once charging is complete, charge is transferred from capacitor 166 to capacitor 116 by closing switch 114 and switch 164. This results in a value of approximately double voltage input 160 at the output of operational amplifier 110. Again, if the result is a logic ‘0’, counter 130 is not incremented and substantially the same process is repeated until the result of a logic ‘1’ is achieved.
Alternatively, on any pass wherein the result of the comparison is a logic ‘1’, counter 130 is incremented. Further, if the result is a logic ‘1’, the negative version of the voltage reference 150 is sampled along with voltage input 160 on the next pass. This is done by closing switch 152, switch 162 and switch 112. This causes charge to build up on reference sample capacitor 156 representing the negative reference voltage, and charge to build up on input sample capacitor 166 representing input voltage 160. The charge from both of the aforementioned capacitors is transferred to integrating capacitor 116 by closing switch 114, switch 154 and switch 164. By continually re-sampling input voltage 160 and sampling the negative voltage reference any time a logic ‘1’ is noted, the following residue will remain for a counter value of X and a number of iterations N:Residue=NVin−XVref.The digital value representing the voltage input is that maintained on counter 130 at the end of the process. The process may be continued for a large number of iterations which would result in a progressively finer resolution. Unfortunately, the number of samples (N) to create a defined output resolution of ADC result 140 increases exponentially. For example, for a ten bit resolution one thousand, twenty-four (210) samples are required. In comparison, for a twenty bit resolution, over one million samples are required (220). Thus, while analog to digital converter 100 is capable of providing accurate results, results exhibiting relatively high resolution require substantial conversion time.
Other approaches for analog to digital conversion exist. Turning to FIG. 1B, a conceptual diagram of a SAR based analog to digital converter 170 is shown. As shown, SAR based analog to digital converter 170 includes a comparator 175 and a shift register 185 that provides an ADC result 190. In operation, a voltage input 180 is compared with one half of a voltage reference 194. If the voltage input is greater than one half of the voltage reference 194, a logic ‘1’ is shifted into shift register 185. Alternatively, if the voltage input is less than one half of the voltage reference 194, a logic ‘0’ is shifted into shift register 185.
Next, if the previous comparison indicated that voltage input 180 is greater than one half of the voltage reference 194, voltage input 180 is compared with one half of the voltage reference 194 augmented with one quarter of the voltage reference 196 by an adder 172 (i.e., voltage input 180 is compared with three quarters of the voltage reference). Again, where the comparison indicates a greater than condition, a logic ‘1’ is shifted into shift register 185. In contrast, if the comparison indicates a less than condition, a logic ‘0’ is shifted into shift register 185.
Alternatively, if the previous comparison indicated that voltage input 180 is less than one half of the voltage reference 194, voltage input 180 is compared with one half of the voltage reference 194 decremented by one quarter of the voltage reference 196 by adder 172 (i.e., voltage input 180 is compared with one quarter of the voltage reference). Again, if the comparison indicates a greater than condition, a logic ‘1’ is shifted into shift register 185. In contrast, if the comparison indicates a less than condition, a logic ‘0’ is shifted into shift register 185. This process is continued for lower order multiples of the voltage reference. As will be appreciated, the aforementioned process is capable of providing ADC result 190 with a very high resolution in a relatively small amount of time. In particular, only a single iteration is required to produce each bit of resolution. For example, for a ten bit resolution ten iterations are required, and for twenty bits of resolution only twenty iterations are required. However, while analog to digital converter 170 is capable of providing quick results, the results are often inaccurate due to noise.
At high operating temperatures, the previously mentioned “leaky” low voltage integrated circuit manufacturing processes result in relatively high leakage currents. This is a serious limitation for the accuracy of an ADC manufactured using such processes. It requires more complicated switches as additional switching modes are introduced. Unfortunately, mixed or hybrid delta-sigma/SAR ADC architectures require more complex switching than ADCs including only delta-sigma architecture or including only SAR architecture.
A serious problem of the hybrid delta-sigma/SAR ADC as described in above mentioned commonly assigned patent application Ser. No. 11/738,566 is the amount of output voltage swing required at the output of the integrator when the hybrid delta-sigma/SAR is operating in its SAR mode. The algorithm for SAR operation using two comparators and a single cycle per SAR bit is:
If (Vresidue > +Vthreshold) Then    Vout = 2*(Vresidue − Vref)Else If (Vresidue < −Vthreshold) Then    Vout = 2*(Vresidue + Vref)Else    Vout = 2*(Vresidue)End IfA different algorithm for use with a single comparator and two cycles per SAR bit is:Cycle 1
If (Vresidue > 0) then  Vout1 = 2*(Vresidue − Vref)Else  Vout1 = 2*(Vresidue)End IfCycle 2Vout2=(Vout1+Vref)
In the foregoing case, Vresidue is the integrator output voltage from the last integration cycle or the previous SAR cycle, Vref is the reference voltage, Vout is the resulting output of the integrator and Vthreshold is the comparator threshold. From the two foregoing algorithms it is clear that for implementation of the algorithm using a single comparator the output swing of the integrator is significantly greater during the SAR mode of operation, due to the multiplication by two and due to the adding or subtracting of a full reference.
The necessary output voltage swing results in an undesirable limitation on the minimum power supply voltage at which the hybrid delta-sigma/SAR can operate. The necessary output voltage swing can be reduced by increasing the number of integration capacitors, but that has the undesired effect of increasing the amount of required integrated circuit chip area and either increasing the quiescent current required in the integrator or having an accordingly longer settling time needed every half cycle for the integrator output voltage to settle to the necessary value with the necessary accuracy.
The conventional method for SAR operation, as described in above mentioned parent patent application Ser. No. 11/738,566, is to perform simultaneous amplification of the residue of the integrator and sampling of the reference. This can achieve one bit resolution in one cycle, but requires additional capacitors to perform the multiplication as the ones used to sample the reference are busy.
Thus, there is an unmet need for a circuit and method which provides a hybrid delta-sigma/SAR ADC which is capable of operation from a reduced power supply voltage.
There also is an unmet need for a circuit and method which provides a hybrid delta-sigma/SAR ADC in which the output voltage swing of an integrator therein is reduced without increasing the amount of integrated circuit chip area required.
There also is an unmet need for a circuit and method which provides a hybrid delta-sigma/SAR ADC in which the output voltage swing of an integrator therein is reduced without increasing the number of integration capacitors or increasing the settling time of the integrator output signal.